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vhdl [2025/12/19 21:40] – [VHDL] 2a00:1028:919d:bcb2:6c0c:6a7a:46d:adc4vhdl [2025/12/19 21:40] (current) – [SDRAM Memory] 2a00:1028:919d:bcb2:6c0c:6a7a:46d:adc4
Line 3: Line 3:
 Verilator https://itsembedded.com/dhd/verilator_1/ Verilator https://itsembedded.com/dhd/verilator_1/
  
-===== SDRAM Memory ===== +SDRAM https://electronics.stackexchange.com/questions/631943/fpga-to-sdram-communication
- +
-https://electronics.stackexchange.com/questions/631943/fpga-to-sdram-communication+
  
 and https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd and https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd
vhdl.txt · Last modified: 2025/12/19 21:40 by 2a00:1028:919d:bcb2:6c0c:6a7a:46d:adc4