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==== FPGA ====

<code vhdl>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------------

package float32 is

--------------------------------------------------------------------------------

type fp32 is record
		sign : std_logic;
		exponent : unsigned(7 downto 0);
		mantissa : unsigned(22 downto 0);
	end record fp32;
	
	type fp32_array is array(natural range<>) of fp32;
	
--------------------------------------------------------------------------------
	
	constant fp32_EXPONENT_OFFSET : unsigned(7 downto 0) := "01111111";
	constant fp32_EXPONENT_OFFSET_INT : integer := 127;
	
	constant fp32_ZERO : fp32 := (
		sign => '0', 
		exponent => (others => '0'), 
		mantissa => (others => '0')
	);

constant fp32_INF  : fp32 := (
		sign => '0', 
		exponent => (others => '1'), 
		mantissa => (others => '0')
	);
	
--------------------------------------------------------------------------------
	
	function fp32_abs_eq (first, second : in fp32) return boolean;
	function fp32_is_nan (first, second : in fp32) return boolean;
	function fp32_gt (first, second: in fp32) return boolean;

--------------------------------------------------------------------------------	
	
	function fp32_from_slv (src : in std_logic_vector(31 downto 0)) return fp32;
	function slv_from_fp32 (src : in fp32) return std_logic_vector;

function fp32_add (first, second: in fp32) return fp32;
	function fp32_sub (first, second: in fp32) return fp32;
	function fp32_mul (first, second: in fp32) return fp32;
	--function fp32_div (first, second: in fp32) return fp32;
	
--------------------------------------------------------------------------------

end float32;

--------------------------------------------------------------------------------

package body float32 is

--------------------------------------------------------------------------------

function fp32_abs_eq (first, second : in fp32) return boolean is
	begin
		return (first.exponent = second.exponent and 
			first.mantissa = second.mantissa);
	end function fp32_abs_eq;
	
	function fp32_is_nan (first, second : in fp32) return boolean is
	begin
		return (first.exponent = fp32_INF.exponent and 
			first.mantissa /= fp32_INF.mantissa);
	end function fp32_is_nan;

--------------------------------------------------------------------------------

function fp32_gt (first, second: in fp32) return boolean is
		variable result : boolean := false;
	begin		
		if first.exponent = fp32_ZERO.exponent and second.exponent = fp32_ZERO.exponent then
		   -- zero > zero
		   result := false; 
	    elsif first.exponent = fp32_ZERO.exponent and second.exponent /= fp32_ZERO.exponent then
		   -- zero > nonzero
		   result := second.sign /= '0'; 
	    elsif first.exponent /= fp32_ZERO.exponent and second.exponent = fp32_ZERO.exponent then
		   -- nonzero > zero
		   result := first.sign = '0'; 
	    else -- if first.exponent /= 0 and second.exponent /= 0 then
		   -- both nonzero
  	       if first.sign = '1' and second.sign = '0' then
			   -- negative > positive
  		       result := false; 
  	       elsif first.sign = '0' and second.sign = '1' then
			   -- positive > negative
  		       result := true; 
		   else
		       -- same sign
  	           if first.exponent > second.exponent then
		          result := true;
  	           elsif first.exponent < second.exponent then
		          result := false;
  	           else
		          result := first.mantissa > second.mantissa;
   	           end if;

if first.sign = '1' then
				  -- both negative
			      result := not result; 
			   end if;
		   end if;
		end if;
		return result; 
	end function fp32_gt;
	 
--------------------------------------------------------------------------------

function fp32_from_slv (src : in std_logic_vector(31 downto 0)) return fp32 is
	begin
		return (sign => src(31), 
			exponent => unsigned(src(30 downto 23)),
			mantissa => unsigned(src(22 downto 0)));
	end function fp32_from_slv;

function slv_from_fp32 (src : in fp32) return std_logic_vector is
	begin
		return src.sign & std_logic_vector(src.exponent) & std_logic_vector(src.mantissa);
	end function slv_from_fp32;

function fp32_mul (first, second: in fp32) return fp32 is
		variable result : fp32 := fp32_ZERO;
		variable buf : unsigned(47 downto 0) := (others => '0');
		variable start : integer := 46;
	begin
	    if first.exponent /= 0 and second.exponent /= 0 then
		   result.sign := first.sign xor second.sign;
		   result.exponent := first.exponent + second.exponent - fp32_EXPONENT_OFFSET;
		   buf := unsigned('1' & first.mantissa) * unsigned('1' & second.mantissa);

-- normalize
		   for i in 47 downto 46 loop
			   if buf(i) = '1' then
				   start := i - 1;
				   exit;
			   end if;
		   end loop;

result.exponent := to_unsigned(to_integer(result.exponent) + start - 45, 8);
    	   result.mantissa := buf(start downto start-22);
		end if;
		return result;
	end function fp32_mul;

--------------------------------------------------------------------------------

function fp32_sum (first, second: in fp32) return fp32 is
        variable result : fp32 := fp32_ZERO;
        variable buf  : unsigned (24 downto 0) := (others => '0');
        variable buf1 : unsigned (24 downto 0) := (others => '0');
        variable buf2 : unsigned (24 downto 0) := (others => '0');
        variable delta : integer := 0;
        variable start : integer := 22;
	variable zero : boolean := true;
    begin
         result.sign := first.sign;
         result.exponent := first.exponent;

buf1 := unsigned("01" & first.mantissa);
         buf2 := unsigned("01" & second.mantissa);

delta := to_integer(first.exponent) - to_integer (second.exponent);
         if delta < 24 then
              if delta /= 0 then
                 buf2 (24-delta downto 0) := buf2 (24 downto delta);
                 buf2 (24 downto 24-delta+1) := (others => '0');
              end if;

if first.sign = second.sign then
                 buf := buf1 + buf2;
              else
                 buf := buf1 - buf2;
              end if;
         end if;

-- normalize
	 for i in 24 downto 0 loop
         	if buf(i) = '1' then
            		start := i;
			zero := false;
			exit;
         	end if;
	 end loop;
	
	if not zero then
        	result.exponent := result.exponent + start - 1 - 22;

if start = 24 then
			result.mantissa(22 downto 0) := buf(23 downto 1);
		-- elsif start = 23 then
		--	result.mantissa(22 downto 0) := buf(22 downto 0);
		elsif start > 0
			result.mantissa(22 downto 23-start) := buf(start-1 downto 0);
		end if;
	end if;
        return result;
    end function fp32_sum;

function fp32_add (first, second: in fp32) return fp32 is
    begin
        if first.exponent = 0 then
            return second;
        elsif second.exponent = 0 then
            return first;
        elsif first.exponent > second.exponent then
            return fp32_sum (first, second);
        elsif first.exponent < second.exponent then
            return fp32_sum (second, first);
	elsif first.mantissa >= second.mantissa then
		return fp32_sum (first, second);
	else
		return fp32_sum (second, first);
        end if;
    end function fp32_add;

function fp32_sub (first, second: in fp32) return fp32 is
        variable temp : fp32 := second;
    begin
        temp.sign := not temp.sign;
		return fp32_add (first, temp);
    end function fp32_sub;

--------------------------------------------------------------------------------

end float32;

--------------------------------------------------------------------------------
</code>

==== Install ====

https://www.linux-magazine.com/Online/Features/Resetting-Passwords-with-SystemRescueCd

https://masoncb.medium.com/using-ventoy-to-install-windows-11-from-a-linux-device-ead91ce729d3

==== WSL ====
https://www.reddit.com/r/bashonubuntuonwindows/comments/15jeuyu/you_can_start_mate_desktop_in_wsl_2_like_this/

<code>
ln -s /dev/null /etc/systemd/system/acpid.service
ln -s /dev/null /etc/systemd/system/acpid.path
apt-get install xwayland glmark2 glmark2-wayland ubuntu-mate-desktop mate-terminal libgl1 libegl1
ln -s /mnt/wslg/runtime-dir/wayland-0* /run/user/$(id -u)
nohup Xwayland -br -ac -noreset :1 &
env DISPLAY=:1 WAYLAND_DISPLAY= mate-session
</code>

==== Hyper-V ====
https://bbs.archlinux.org/viewtopic.php?id=271255

solved this problem by forcing X to use the fbdev driver and providing the framebuffer device id like so.
Create the file:

<code>
/etc/X11/xorg.conf.d/99-fbdev.conf
</code>

Add the following:

<code>
Section "Device"
        Identifier  "Card0"
        Driver      "fbdev"
        BusID       "PCI:0:8:0"
EndSection
</code>

Please mind that your BusID might be different. You can just run

<code>
Xorg -configure
</code>

which will create /root/xorg.conf.new. Then look in this file for your BusID and act accordingly if it differs.

==== Remote ====

<code>
mc sh://pc1 sh://pc2

mcedit sh://pc1/~/.config/mc/hotlist
mcedit sh://pc1/home/user/.config/mc/hotlist

mcdiff sh://pc1/home/user/.config/mc/hotlist sh://pc2/home/user/.config/mc/hotlist
</code>

https://gede.dexar.se/uploads/tutorials/arm_debugging/

QSsh https://github.com/sandsmark/QSsh

https://github.com/lvklabs/QSsh/blob/master/src/libs/ssh/sftpfilesystemmodel.h

https://github.com/artoka/libsshqt

==== Windows installation ====

https://www.tenforums.com/tutorials/94479-clean-install-windows-10-without-dvd-usb-flash-drive.html

https://www.tenforums.com/tutorials/84331-apply-windows-image-using-dism-instead-clean-install.html

https://www.tenforums.com/tutorials/103428-create-winpe-usb-iso.html

https://learn.microsoft.com/en-us/windows-hardware/manufacture/desktop/dism-image-management-command-line-options-s14?view=windows-11#apply-image

google : windows installation from media copied to ntfs partition

https://wimlib.net/man1/wimapply.html

https://schneegans.de/windows/unattend-generator/

==== FPGA ====

https://schaumont.dyn.wpi.edu/ece4530f19/lectures/lecture13-notes.html

https://github.com/stnolting/neorv32

https://stnolting.github.io/neorv32/ug/#_ghdl_simulation

neorv32-verilog https://github.com/stnolting/neorv32-verilog

https://github.com/stnolting/neorv32-freertos

https://docs.zephyrproject.org/latest/boards/others/neorv32/doc/index.html

https://section5.ch/index.php/2019/10/24/risc-v-in-the-loop/

https://github.com/aolofsson/awesome-opensource-hardware-repos?tab=readme-ov-file#connectivity

https://ejaaskel.dev/running-zephyr-rtos-on-neorv32-soft-processor/

https://www.dejazzer.com/eigenpi/digital_camera/digital_camera.html

https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#running-linux

https://communicity-docs.readthedocs.io/en/latest/src/communicity_toolbox/toolbox/Models/face_detector_retinaface/README.html

https://github.com/kingardor/retinaface-onnx

MobileNet-Tiny  https://nitheshsinghsanjay.github.io/

https://github.com/NitheshSinghSanjay/Deep-Neural-Network-based-Real-Time-Object-Detection-for-Raspberry-Pi-and-non-GPU-devices

https://learnopencv.com/understanding-convolutional-neural-networks-cnn/

https://github.com/onnx/models

https://github.com/StanislasBertrand/RetinaFace-tf2

https://github.com/serengil/retinaface

https://github.com/ddfabbro/tiny-retinaface

https://daj.medium.com/how-to-inspect-a-pre-trained-tensorflow-model-5fd2ee79ced0

MobileNet-in-FPGA https://github.com/ZFTurbo/MobileNet-in-FPGA

https://github.com/meiniKi/RV32I_SC_Logisim

[[https://www.fruugo.cz/pro-tang-konzole-60k-mini-fpga-vyvojova-deska-high-perf-kompaktni-retro-herni-konzole-pro-raspberry/p-420697437-886391400?language=cs&ac=google&asc=pmax&gad_source=1&gad_campaignid=19591856071&gclid=EAIaIQobChMIgoPlnNepkAMVx5SDBx2b3jNaEAYYASABEgKJ0fD_BwE|Tang Console]]

Verilator https://github.com/aignacio/riscv_verilator_model

VexRiscv https://github.com/SpinalHDL/VexRiscv

gdb Verilator https://hackaday.io/project/185019-boxlambda/log/210296-hello-debugger

Bruno Levy https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV

https://github.com/YosysHQ/nextpnr

https://hackernoon.com/getting-started-using-open-source-fpga-tools

https://blog.richliu.com/2025/08/27/6391/build-risc-v-on-ubuntu-linux/

https://github.com/Charrin/RetinaFace-Cpp

https://github.com/clancylian/retinaface

Viola-Jones https://github.com/eigenpi/Face-Detection-on-FPGA

tinygrad micrograd

https://github.com/cornell-zhang/facedetect-fpga

https://github.com/Linzaer/Ultra-Light-Fast-Generic-Face-Detector-1MB

TinyFPGA https://github.com/tinyfpga/TinyFPGA-BX/blob/master/examples/picosoc/picorv32.v

Yosys https://github.com/YosysHQ

IceStudio https://github.com/FPGAwars/icestudio/

rvapo https://gitlab.fel.cvut.cz/otrees/fpga/rvapo-vhdl

TangNano 9K https://github.com/sipeed/TangNano-9K-example/tree/main/picotiny

PicoRV32 https://github.com/YosysHQ/picorv32

PicoRV32 https://github.com/clairexen/picorv

Designing a RISC-V CPU in VHDL https://domipheus.com/blog/rpu-series-quick-links/

cosim (qemu and ghdl) https://github.com/giorby/cosim

https://github.com/zangman/de10-nano

DE-10 https://github.com/ikwzm/FPGA-SoC-Linux

https://github.com/thinkoco/de10-nano-riscv

==== RetinaFace ====

RetinaFace_int.onnx https://huggingface.co/amd/retinaface/tree/main/weights

mobilenet0.25_Final.pth  Resnet50_Final.pth https://github.com/elliottzheng/face-detection/releases

https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/tag/v1.0
weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5

retinaface-resnet50.onnx https://huggingface.co/TheEeeeLin/HivisionIDPhotos_matting/tree/main

RetinaFace-Res50.h5 https://huggingface.co/felixrosberg/RetinaFace/tree/main

resnet50.pth https://huggingface.co/felixrosberg/RetinaFace/tree/main

https://github.com/RangiLyu/nanodet

https://learnopencv.com/what-is-face-detection-the-ultimate-guide/

https://jonathan-hui.medium.com/ssd-object-detection-single-shot-multibox-detector-for-real-time-processing-9bd8deac0e06
==== Onnx ====

https://github.com/fdwr/Onnx2Text

https://github.com/mlomb/onnx2code

https://github.com/kraiskil/onnx2c

inference_onnx.py, convert .pth to .onnx https://github.com/kingardor/retinaface-onnx

https://onnxruntime.ai/docs/tutorials/api-basics.html

https://github.com/onnx/models/tree/main/validated/vision/classification/resnet/model

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