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vhdl [2025/12/13 20:19] – [NIOS] 2a00:1028:919d:bcb2:740a:d1bf:c035:85fbvhdl [2025/12/17 21:46] (current) – [Quartus] 147.32.8.31
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 https://www.mouser.com/datasheet/2/598/DE25_Standard_User_manual_revC-3680989.pdf https://www.mouser.com/datasheet/2/598/DE25_Standard_User_manual_revC-3680989.pdf
  
 +===== DE-10 Control Panel ====
 +
 +ControlPanel/Quartus mem_dq
 +
 +DE10-Standard_User_manual.pfd
 +
 +**Generate FPGA Configure Files: fpga.dtbo and soc_system.rbf**
 +
 +<code>
 +dtc -O dtb -o fpga.dtbo -b 0 -@ fpga.dts
 +</code>
 +
 +**Apply FPGA Configure Files: fpga.dtbo and soc_system.rbf**
 +
 +<code>
 +mount –t configfs configfs /config
 +mkdir /config/device-tree/overlays/test
 +echo fpga.dtbo > /config/device-tree/overlays/test/path
 +</code>
 +
 +
 +The LED0 on the FPGA will blink
 ===== DE-10 Standard ===== ===== DE-10 Standard =====
  
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 Initialization: You can initialize the RAM contents using a Memory Initialization File (.mif) or Hexadecimal file (.hex) by following the Quartus settings to include initialization data in the bitstream.  Initialization: You can initialize the RAM contents using a Memory Initialization File (.mif) or Hexadecimal file (.hex) by following the Quartus settings to include initialization data in the bitstream. 
  
 +
 +==== MEMORY AVL ====
 +
 +<code>
 +library ieee;
 +use ieee.std_logic_1164.all;
 +use ieee.numeric_std.all;
 +
 +entity DDR_Access is
 +    port (
 +        clk         : in std_logic;
 +        reset_n     : in std_logic;
 +        -- DDR memory interface signals (provided by the memory controller IP)
 +        avl_address : out std_logic_vector(31 downto 0);
 +        avl_read    : out std_logic;
 +        avl_write   : out std_logic;
 +        avl_writedata : out std_logic_vector(31 downto 0);
 +        avl_readdata  : in std_logic_vector(31 downto 0);
 +        avl_wait    : in std_logic;
 +        -- Additional signals as needed
 +        -- For example, a simple state machine control signals
 +        start       : in std_logic
 +    );
 +end entity;
 +
 +architecture Behavioral of DDR_Access is
 +    type state_type is (IDLE, READ, WRITE, DONE);
 +    signal state : state_type := IDLE;
 +
 +    -- Example signals
 +    signal address_reg : std_logic_vector(31 downto 0) := (others => '0');
 +    signal data_reg    : std_logic_vector(31 downto 0) := (others => '0');
 +    signal read_req    : std_logic := '0';
 +    signal write_req   : std_logic := '0';
 +
 +begin
 +    process(clk, reset_n)
 +    begin
 +        if reset_n = '0' then
 +            state <= IDLE;
 +            avl_address <= (others => '0');
 +            avl_read <= '0';
 +            avl_write <= '0';
 +            avl_writedata <= (others => '0');
 +        elsif rising_edge(clk) then
 +            case state is
 +                when IDLE =>
 +                    if start = '1' then
 +                        -- Initiate a read or write
 +                        address_reg <= x"0000_1000"; -- Example address
 +                        data_reg <= x"DEADBEEF"; -- Example data
 +                        avl_address <= address_reg;
 +                        avl_writedata <= data_reg;
 +                        avl_write <= '1';
 +                        avl_read <= '0';
 +                        state <= WRITE;
 +                    end if;
 +
 +                when WRITE =>
 +                    if avl_wait = '0' then
 +                        avl_write <= '0';
 +                        state <= IDLE;
 +                    end if;
 +
 +                when others =>
 +                    null;
 +            end case;
 +        end if;
 +    end process;
 +
 +end Behavioral;
 +</code>
 ==== DSP ==== ==== DSP ====
  
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 PROCESSOR https://github.com/NTP17/AKVP_x09 PROCESSOR https://github.com/NTP17/AKVP_x09
-==== NIOS ==== 
  
 VGA https://github.com/vacer25/Nios_II-VGA-Out VGA https://github.com/vacer25/Nios_II-VGA-Out
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 FPGA SDRAM Communication https://github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Avalon-MM-Host-Master-Component-Part-3.md FPGA SDRAM Communication https://github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Avalon-MM-Host-Master-Component-Part-3.md
 +
 +https://github.com/zangman/de10-nano/blob/master/docs/Write-Linux-Driver.md
 +
 +https://github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Avalon-MM-Host-Master-Component-Part-1.md
 +
 +https://github.com/zangman/de10-nano/blob/master/docs/Simple-Hardware-Adder_-Primer-on-Avalon-Memory-Map-Interface.md
 +
 +
 +0x40000000 https://ftp.intel.com/Public/Pub/fpgaup/pub/Intel_Material/18.1/Computer_Systems/DE10-Standard/DE10-Standard_Computer_NiosII.pdf
 +
 +
 +CD https://download.terasic.com/downloads/cd-rom/de10-standard/Linux/
 +
 +https://www.altera.com/downloads/fpga-development-tools/quartus-prime-lite-edition-design-software-version-16-1-b196-linux
 +
 +https://www.altera.com/downloads/fpga-development-tools/quartus-prime-lite-edition-design-software-version-21-1-linux
 +
 +https://sudonull.com/post/68502-Experience-using-the-FPGA-board-DE10-Standard-and-DMA-PL330
 +
vhdl.1765657189.txt.gz · Last modified: 2025/12/13 20:19 by 2a00:1028:919d:bcb2:740a:d1bf:c035:85fb