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--- vhdl [2025/10/29 19:56] – [Matrix Multiply] 147.32.8.31
+++ vhdl [2025/10/29 20:27] (current) – [SDRAM Memory] 147.32.8.31
@@ Line 243: / Line 243: @@
     );
 end entity;
-===== DDR Memory =====
 architecture Behavioral of sdram_controller is
@@ Line 392: / Line 390: @@
 end Behavioral;
 </code>
-==== ghdl memory ====
-<code vhdl>
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-entity ram is
-    generic (
-        DATA_WIDTH : integer := 8;  -- Width of data bus
-        ADDR_WIDTH : integer := 4   -- Width of address bus (16 addresses)
-    );
-    port (
-        clk      : in std_logic;
-        we       : in std_logic; -- Write enable
-        addr     : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        data_in  : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
-    );
-end entity;
-architecture Behavioral of ram is
-    type mem_type is array (0 to 2**ADDR_WIDTH - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-    signal mem : mem_type := (others => (others => '0'));
-begin
-    process(clk)
-    begin
-        if rising_edge(clk) then
-            if we = '1' then
-                -- Write operation
-                mem(to_integer(unsigned(addr))) <= data_in;
-            end if;
-            -- Read operation
-            data_out <= mem(to_integer(unsigned(addr)));
-        end if;
-    end process;
-end architecture;
-</code>
-<code vhdl>
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-entity tb_ram is
-end entity;
-architecture Behavioral of tb_ram is
-    signal clk      : std_logic := '0';
-    signal we       : std_logic := '0';
-    signal addr     : std_logic_vector(3 downto 0);
-    signal data_in  : std_logic_vector(7 downto 0);
-    signal data_out : std_logic_vector(7 downto 0);
-    component ram
-        generic (
-            DATA_WIDTH : integer := 8;
-            ADDR_WIDTH : integer := 4
-        );
-        port (
-            clk      : in std_logic;
-            we       : in std_logic;
-            addr     : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-            data_in  : in std_logic_vector(DATA_WIDTH-1 downto 0);
-            data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
-        );
-    end component;
-begin
-    uut: ram
-        port map (
-            clk => clk,
-            we => we,
-            addr => addr,
-            data_in => data_in,
-            data_out => data_out
-        );
-    -- Clock generation
-    clk_process : process
-    begin
-        while true loop
-            clk <= '0';
-            wait for 10 ns;
-            clk <= '1';
-            wait for 10 ns;
-        end loop;
-    end process;
-    -- Test sequence
-    stim_proc: process
-    begin
-        -- Write data to address 0x1
-        addr <= "0001";
-        data_in <= "10101010";
-        we <= '1';
-        wait for 20 ns;
-        -- Disable write
-        we <= '0';
-        wait for 20 ns;
-        -- Read from address 0x1
-        addr <= "0001";
-        wait for 20 ns;
-        -- Write data to address 0x2
-        addr <= "0010";
-        data_in <= "11001100";
-        we <= '1';
-        wait for 20 ns;
-        -- Disable write
-        we <= '0';
-        wait for 20 ns;
-        -- Read from address 0x2
-        addr <= "0010";
-        wait for 20 ns;
-        wait;
-    end process;
-end architecture;
-</code>
-<code>
-Compile:            ghdl -a ram.vhd tb_ram.vhd
-Elaborate:          ghdl -e tb_ram
-Run the simulation: ghdl -r tb_ram --wave=wave.ghw
-View waveform:      gtkwave wave.ghw
-</code>
 ==== Matrix Multiply =====
@@ Line 809: / Line 675: @@
 end Behavioral;
 </code>
+==== ghdl memory ====
+<code vhdl>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity ram is
+    generic (
+        DATA_WIDTH : integer := 8;  -- Width of data bus
+        ADDR_WIDTH : integer := 4   -- Width of address bus (16 addresses)
+    );
+    port (
+        clk      : in std_logic;
+        we       : in std_logic; -- Write enable
+        addr     : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        data_in  : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+architecture Behavioral of ram is
+    type mem_type is array (0 to 2**ADDR_WIDTH - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+    signal mem : mem_type := (others => (others => '0'));
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if we = '1' then
+                -- Write operation
+                mem(to_integer(unsigned(addr))) <= data_in;
+            end if;
+            -- Read operation
+            data_out <= mem(to_integer(unsigned(addr)));
+        end if;
+    end process;
+end architecture;
+</code>
+<code vhdl>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity tb_ram is
+end entity;
+architecture Behavioral of tb_ram is
+    signal clk      : std_logic := '0';
+    signal we       : std_logic := '0';
+    signal addr     : std_logic_vector(3 downto 0);
+    signal data_in  : std_logic_vector(7 downto 0);
+    signal data_out : std_logic_vector(7 downto 0);
+    component ram
+        generic (
+            DATA_WIDTH : integer := 8;
+            ADDR_WIDTH : integer := 4
+        );
+        port (
+            clk      : in std_logic;
+            we       : in std_logic;
+            addr     : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+            data_in  : in std_logic_vector(DATA_WIDTH-1 downto 0);
+            data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+        );
+    end component;
+begin
+    uut: ram
+        port map (
+            clk => clk,
+            we => we,
+            addr => addr,
+            data_in => data_in,
+            data_out => data_out
+        );
+    -- Clock generation
+    clk_process : process
+    begin
+        while true loop
+            clk <= '0';
+            wait for 10 ns;
+            clk <= '1';
+            wait for 10 ns;
+        end loop;
+    end process;
+    -- Test sequence
+    stim_proc: process
+    begin
+        -- Write data to address 0x1
+        addr <= "0001";
+        data_in <= "10101010";
+        we <= '1';
+        wait for 20 ns;
+        -- Disable write
+        we <= '0';
+        wait for 20 ns;
+        -- Read from address 0x1
+        addr <= "0001";
+        wait for 20 ns;
+        -- Write data to address 0x2
+        addr <= "0010";
+        data_in <= "11001100";
+        we <= '1';
+        wait for 20 ns;
+        -- Disable write
+        we <= '0';
+        wait for 20 ns;
+        -- Read from address 0x2
+        addr <= "0010";
+        wait for 20 ns;
+        wait;
+    end process;
+end architecture;
+</code>
+<code>
+Compile:            ghdl -a ram.vhd tb_ram.vhd
+Elaborate:          ghdl -e tb_ram
+Run the simulation: ghdl -r tb_ram --wave=wave.ghw
+View waveform:      gtkwave wave.ghw
+</code>
+==== GHDL FLI ====
+<code vhdl>
+library ieee;
+use ieee.std_logic_1164.all;
+entity testbench is
+end entity;
+architecture sim of testbench is
+    -- Declare external procedure
+    procedure external_procedure(signal_value : inout std_logic_vector(7 downto 0));
+    -- Import the procedure from C
+    attribute foreign of external_procedure : procedure is "ghdl_fli_example";
+    signal data : std_logic_vector(7 downto 0) := (others => '0');
+begin
+    process
+    begin
+        wait for 10 ns;
+        external_procedure(data);
+        wait;
+    end process;
+end architecture;
+</code>
+<code c>
+#include <stdio.h>
+#include "ghdl_fli.h"  // GHDL FLI header
+// This function will be called from VHDL
+void ghdl_fli_example (void *args) {
+    // args points to the signal
+    // For simplicity, assume args is a pointer to an array of 8 chars
+    unsigned char *signal_value = (unsigned char *) args;
+    printf("C: Received signal value: 0x%02X", *signal_value);
+    // Modify the signal (e.g., increment)
+    *signal_value = (*signal_value + 1) & 0xFF;
+    printf("C: Modified signal value to: 0x%02X", *signal_value);
+}
+</code>
+<code>
+gcc -shared -fPIC -o ghdl_fli_example.so ghdl_fli_example.c
+ghdl -a testbench.vhd
+ghdl -Wl,ghdl_fli_example.so -e testbench
+ghdl -r testbench --stop-time=50ns
+</code>
+https://github.com/Paebbels/JSON-for-VHDL