vhdl
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| Both sides previous revisionPrevious revision | |||
| vhdl [2025/12/21 20:18] – [Avalon MM] 2a00:1028:919d:bcb2:7542:e925:63c7:87da | vhdl [2025/12/21 20:22] (current) – [Avalon MM] 2a00:1028:919d:bcb2:7542:e925:63c7:87da | ||
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| Line 1129: | Line 1129: | ||
| < | < | ||
| - | # ------------------------------------------------------------- | + | # Load existing |
| - | # Create | + | load_system |
| - | # ------------------------------------------------------------- | + | |
| - | # create_system | + | |
| - | + | ||
| - | # set_project_property DEVICE_FAMILY " | + | |
| - | # set_project_property HIDE_FROM_QUARTUS_SETTINGS 1 | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # Add instances | + | # Add your custom component |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | |||
| - | # HPS (Cyclone V SoC) | ||
| - | # Make sure the IP name matches your Quartus/ | ||
| - | # Common name: " | ||
| - | add_instance hps_0 altera_hps | ||
| - | |||
| - | # Your custom DDR3 burst master with control registers | ||
| - | # This assumes you already have ddr3_burst_master_ctrl_hw.tcl and .vhd | ||
| - | # in the IP search path. | ||
| add_instance ddr3_burst_master_ctrl_0 ddr3_burst_master_ctrl | add_instance ddr3_burst_master_ctrl_0 ddr3_burst_master_ctrl | ||
| - | |||
| - | # (Optional) JTAG UART so HPS or Nios can print messages | ||
| - | # add_instance jtag_uart_0 altera_avalon_jtag_uart | ||
| - | |||
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # Clock & reset connections | + | # Connect clocks and resets from HPS |
| - | # Use HPS user clock & reset to drive your custom component. | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | |||
| - | # Clock: hps_0.h2f_user0_clock -> ddr3_burst_master_ctrl_0.clk | ||
| add_connection hps_0.h2f_user0_clock ddr3_burst_master_ctrl_0.clk | add_connection hps_0.h2f_user0_clock ddr3_burst_master_ctrl_0.clk | ||
| - | + | add_connection hps_0.h2f_reset | |
| - | # Reset: hps_0.h2f_reset -> ddr3_burst_master_ctrl_0.reset | + | |
| - | add_connection hps_0.h2f_reset ddr3_burst_master_ctrl_0.reset | + | |
| - | + | ||
| - | # JTAG UART clock/reset (also from HPS user clock/ | + | |
| - | # add_connection hps_0.h2f_user0_clock jtag_uart_0.clk | + | |
| - | # add_connection hps_0.h2f_reset | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # Avalon-MM connections | + | # Connect control registers to HPS lightweight bridge |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | |||
| - | # 1) HPS lightweight master -> control registers (s_slave) | ||
| - | # HPS Linux can access your registers via the LW bridge. | ||
| add_connection hps_0.h2f_lw_axi_master ddr3_burst_master_ctrl_0.s_slave | add_connection hps_0.h2f_lw_axi_master ddr3_burst_master_ctrl_0.s_slave | ||
| - | # 2) Burst master -> HPS SDRAM (f2h_sdram0_data) | + | # Assign address window for control registers |
| - | # Your burst engine reads/writes HPS DDR3 used by Linux. | + | set_connection_parameter_value \ |
| - | add_connection | + | |
| - | + | | |
| - | # 3) HPS lightweight master -> JTAG UART (for debug) | + | |
| - | add_connection hps_0.h2f_lw_axi_master jtag_uart_0.avalon_jtag_slave | + | |
| + | set_connection_parameter_value \ | ||
| + | hps_0.h2f_lw_axi_master/ | ||
| + | span 0x10 | ||
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # Address map | + | # Connect burst master to HPS DDR3 |
| - | # Only SLAVES get address ranges. | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | + | add_connection | |
| - | # Control registers window in LW bridge: | + | |
| - | # base: 0x0000_8000 | + | |
| - | # span: 0x0000_0010 (16 bytes: 4 registers x 4 bytes) | + | |
| - | set_connection_parameter_value hps_0.h2f_lw_axi_master/ | + | |
| - | set_connection_parameter_value | + | |
| - | + | ||
| - | # JTAG UART window: | + | |
| - | # base: 0x0000_9000 | + | |
| - | # span: 0x0000_0010 | + | |
| - | # set_connection_parameter_value hps_0.h2f_lw_axi_master/ | + | |
| - | # set_connection_parameter_value hps_0.h2f_lw_axi_master/ | + | |
| - | + | ||
| - | # NOTE: Do NOT assign an address to ddr3_burst_master_ctrl_0.m_master. | + | |
| - | # It is a MASTER; only slaves (like f2h_sdram0_data) have address windows. | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # Export | + | # Export |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | + | add_interface burst_status conduit end | |
| - | # Export HPS external interfaces (clocks, DDR, I/O, etc.) | + | set_interface_property burst_status EXPORT_OF ddr3_burst_master_ctrl_0.status |
| - | # The names must match the interface names of the HPS IP. | + | |
| - | # These exports let your top-level .qsys entity expose the HPS pins. | + | |
| - | + | ||
| - | # add_interface hps_io conduit end | + | |
| - | # set_interface_property hps_io EXPORT_OF hps_0.hps_io | + | |
| - | + | ||
| - | # add_interface hps_reset reset end | + | |
| - | # set_interface_property hps_reset EXPORT_OF hps_0.hps_reset | + | |
| - | + | ||
| - | # add_interface hps_clock clock end | + | |
| - | # set_interface_property hps_clock EXPORT_OF hps_0.hps_clock | + | |
| - | + | ||
| - | + | ||
| - | # Export your custom status (done/ | + | |
| - | # add_interface burst_status conduit end | + | |
| - | # set_interface_property burst_status EXPORT_OF ddr3_burst_master_ctrl_0.status | + | |
| - | + | ||
| - | # (Optional) export the HPS-to-FPGA interrupt if you add an IRQ later | + | |
| - | # add_interface burst_irq interrupt end | + | |
| - | # set_interface_property burst_irq EXPORT_OF ddr3_burst_master_ctrl_0.irq | + | |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | # System done | + | # Save updated system |
| # ------------------------------------------------------------- | # ------------------------------------------------------------- | ||
| - | save_system soc_system | + | save_system soc_system.qsys |
| </ | </ | ||
vhdl.txt · Last modified: 2025/12/21 20:22 by 2a00:1028:919d:bcb2:7542:e925:63c7:87da
